Architecture Analysis

Embarking on designing the next generation x 86 processor cores, when, AMD's engineers considered necessary to achieve the core area of power consumption and optimization, and development of PC applications also allow engineers must find a new path, it is possible between different cores maximize peak bandwidth, and through sharing module to take advantage of every square millimeter of the core area. The end result is the ability to efficiently optimize the dual-core modular resources. Integer pipeline, a data caching frequently used features in each core has a separate functional units, prefetch, decode,drive bulldozers， floating-point pipeline, the secondary cache and other functional units in the two core in shared use. This design allows each core can use when you need a larger, higher-performance functional unit than each core has its own small independent functional units more economical core area. This design concept is a direct manifestation of the core area. Eight-core Bulldozer is AMD manufactured the history of the largest chip integrates approximately 1.2 billion transistors, but the application, the core area through the rational allocation of functional units,construction earthmover as well as the new 32nm SOI process is controlled only to 315 mm2, more than six-core, 45nm process Phenom II X6 9 percent smaller than the quad-core, 32nm HKMG technology Sandy Bridge only 46% larger